Internal Block Diagram
Open Lamp Regulation
Ct1
1
3
S6520
OLR1
Oscillator1
+
+
-
Vref
9
+
-
Vref
regulation signal
to COMP1, COMP2
14
OLR2
Vcc
Ct2
15
+
-
Vref
Oscillator2
5V Vref
7V Vz
Internal
bias
ena
Enable Switch
+
-
1.4V
6
ENA
CMP1
FB1
5
4
ADIM
SS
Amplifier 1
-
+
+
+
Vref
iss
Comparator 1
-
+
+
Output 1
7
OUT1
11
2
FB2
13
Vref
Amplifier 2
+
+
-
+
Comparator 2
-
+
+
delay timer
Output 2
10
OUT2
CMP2
GND
12
8
Shut Down Signal to Output
Q
S
R
10us
+
+
-
from FB1
from FB2
n*Vref
16
reset signal from bias
REF
Short Circuit Protection
PIN Collection
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
CT1
SS
OLR1
FB1
CMP1
ENA
OUT1
GND
VCC
OUT2
ADIM
CMP2
FB2
OLR2
CT2
REF
I/O
I
I
I
I
-
I
O
-
I
O
-
-
I
I
I
O
Pin Function Description
Frequency Trimming Capacitor for Main Frequency Setting 1
Initial Soft Start
Open Lamp Regulation 1
Feedback 1 (Error Amplifier Negative Input)
Error Amplifier Output 1
ON/OFF Control Pin. TTL Signal is Applicable.
Output Drive1
Ground
Supply Voltage
Output Drive 2
Analog Dimming Input
Error Amplifier Output 2
Feedback 2 (Error Amplifier Negative Input)
Open Lamp Regulation 2
Frequency Trimming Capacitor for Main Frequency Setting 2
Reference Voltage (VREF) = 5V
KSI-8019-000
2
AUK [ AUK CORP ]
