欢迎访问ic37.com |
会员登录 免费注册
发布采购

MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
 浏览型号MEGA128CAN的Datasheet PDF文件第124页浏览型号MEGA128CAN的Datasheet PDF文件第125页浏览型号MEGA128CAN的Datasheet PDF文件第126页浏览型号MEGA128CAN的Datasheet PDF文件第127页浏览型号MEGA128CAN的Datasheet PDF文件第129页浏览型号MEGA128CAN的Datasheet PDF文件第130页浏览型号MEGA128CAN的Datasheet PDF文件第131页浏览型号MEGA128CAN的Datasheet PDF文件第132页  
In phase and frequency correct PWM mode, the compare units allow generation of  
PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a  
non-inverted PWM and an inverted PWM output can be generated by setting the  
COMnx1:0 to three (See Table on page 132). The actual OCnx value will only be visible  
on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The  
PWM waveform is generated by setting (or clearing) the OCnx Register at the compare  
match between OCRnx and TCNTn when the counter increments, and clearing (or set-  
ting) the OCnx Register at compare match between OCRnx and TCNTn when the  
counter decrements. The PWM frequency for the output when using phase and fre-  
quency correct PWM can be calculated by the following equation:  
fclk_I/O  
fOCnxPFCPWM = ---------------------------  
2 N TOP  
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).  
The extreme values for the OCRnx Register represents special cases when generating  
a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to  
BOTTOM the output will be continuously low and if set equal to TOP the output will be  
set to high for non-inverted PWM mode. For inverted PWM the output will have the  
opposite logic values.  
Timer/Counter Timing  
Diagrams  
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore  
shown as a clock enable signal in the following figures. The figures include information  
on when interrupt flags are set, and when the OCRnx Register is updated with the  
OCRnx buffer value (only for modes utilizing double buffering). Figure 57 shows a timing  
diagram for the setting of OCFnx.  
Figure 57. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling  
clkI/O  
clkTn  
(clkI/O/1)  
TCNTn  
OCRnx  
OCFnx  
OCRnx - 1  
OCRnx  
OCRnx + 1  
OCRnx + 2  
OCRnx Value  
Figure 58 shows the same timing data, but with the prescaler enabled.  
128  
AT90CAN128  
4250E–CAN–12/04  
 复制成功!