AT90CAN128
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to
0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM
resolution in bits can be calculated by using the following equation:
log(TOP + 1)
RFPWM = ----------------------------------
log(2)
In fast PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in
ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is
shown in Figure 54. The figure shows fast PWM mode when OCRnA or ICRn is used to
define TOP. The TCNTn value is in the timing diagram shown as a histogram for illus-
trating the single-slope operation. The diagram includes non-inverted and inverted PWM
outputs. The small horizontal line marks on the TCNTn slopes represent compare
matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a com-
pare match occurs.
Figure 54. Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
OCnx
1
2
3
4
5
6
7
8
Period
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In
addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when
either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are
enabled, the interrupt handler routine can be used for updating the TOP and compare
values.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the Compare Registers. If the TOP value is lower
than any of the Compare Registers, a compare match will never occur between the
TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining
the TOP value. The ICRn Register is not double buffered. This means that if ICRn is
changed to a low value when the counter is running with none or a low prescaler value,
there is a risk that the new ICRn value written is lower than the current value of TCNTn.
The result will then be that the counter will miss the compare match at the TOP value.
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4250E–CAN–12/04
ATMEL [ ATMEL ]
