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MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
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AT90CAN128  
Compare Output Mode and  
Waveform Generation  
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM  
modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no  
action on the OCnx Register is to be performed on the next compare match. For com-  
pare output actions in the non-PWM modes refer to Table 60 on page 131. For fast  
PWM mode refer to Table 61 on page 132, and for phase correct and phase and fre-  
quency correct PWM refer to Table 62 on page 132.  
A change of the COMnx1:0 bits state will have effect at the first compare match after the  
bits are written. For non-PWM modes, the action can be forced to have immediate effect  
by using the FOCnx strobe bits.  
Modes of Operation  
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare  
pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and  
Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect  
the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0  
bits control whether the PWM output generated should be inverted or not (inverted or  
non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the out-  
put should be set, cleared or toggle at a compare match (See “Compare Match Output  
Unit” on page 120 )  
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 128.  
Normal Mode  
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the  
counting direction is always up (incrementing), and no counter clear is performed. The  
counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and  
then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-  
flow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.  
The TOVn flag in this case behaves like a 17th bit, except that it is only set, not cleared.  
However, combined with the timer overflow interrupt that automatically clears the TOVn  
flag, the timer resolution can be increased by software. There are no special cases to  
consider in the Normal mode, a new counter value can be written anytime.  
The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-  
mum interval between the external events must not exceed the resolution of the counter.  
If the interval between events are too long, the timer overflow interrupt or the prescaler  
must be used to extend the resolution for the capture unit.  
The Output Compare units can be used to generate interrupts at some given time. Using  
the Output Compare to generate waveforms in Normal mode is not recommended,  
since this will occupy too much of the CPU time.  
Clear Timer on Compare  
Match (CTC) Mode  
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn  
Register are used to manipulate the counter resolution. In CTC mode the counter is  
cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0  
= 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the  
counter, hence also its resolution. This mode allows greater control of the compare  
match output frequency. It also simplifies the operation of counting external events.  
The timing diagram for the CTC mode is shown in Figure 53. The counter value  
(TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then  
counter (TCNTn) is cleared.  
121  
4250E–CAN–12/04  
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