ATmega8(L)
Register Summary (Continued)
Address
0x01 (0x21)
0x00 (0x20)
Name
TWSR
TWBR
Bit 7
TWS7
Bit 6
TWS6
Bit 5
TWS5
Bit 4
TWS4
Bit 3
TWS3
Bit 2
–
Bit 1
TWPS1
Bit 0
TWPS0
Page
173
171
Two-wire Serial Interface Bit Rate Register
Notes:
1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
9
2486QS–AVR–10/06
ATMEL [ ATMEL CORPORATION ]
