ATMEGA16L-8PU 参数 Datasheet PDF下载

ATmega16(L)

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to

for details on operation of the Watchdog Timer.

Figure 20.

Watchdog Reset During Operation

CC

CK

MCU Control and

Status Register –

MCUCSR

The MCU Control and Status Register provides information on which reset source caused an

MCU Reset.

Bit

7

JTD

Read/Write

Initial Value

R/W

0

6

ISC2

R/W

0

5

–

R

0

4

JTRF

R/W

3

WDRF

R/W

2

BORF

R/W

See Bit Description

1

EXTRF

R/W

0

PORF

R/W

MCUCSR

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUCSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

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