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ATMEGA8A-PU 参数 Datasheet PDF下载

ATMEGA8A-PU图片预览
型号: ATMEGA8A-PU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位具有8K字节的系统内可编程闪存 [8-bit with 8K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管异步传输模式PCATM时钟
文件页数/大小: 307 页 / 6804 K
品牌: ATMEL [ ATMEL ]
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ATmega8A  
6.3.1  
SREG – The AVR Status Register  
Bit  
7
I
6
T
5
H
4
S
3
V
2
N
1
Z
0
C
R/W  
0
SREG  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
• Bit 7 – I: Global Interrupt Enable  
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-  
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable  
Register is cleared, none of the interrupts are enabled independent of the individual interrupt  
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by  
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by  
the application with the SEI and CLI instructions, as described in the Instruction Set Reference.  
• Bit 6 – T: Bit Copy Storage  
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-  
nation for the operated bit. A bit from a register in the Register File can be copied into T by the  
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the  
BLD instruction.  
• Bit 5 – H: Half Carry Flag  
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful  
in BCD arithmetic. See the “Instruction Set Description” for detailed information.  
• Bit 4 – S: Sign Bit, S = N V  
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement  
Overflow Flag V. See the “Instruction Set Description” for detailed information.  
• Bit 3 – V: Two’s Complement Overflow Flag  
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the  
“Instruction Set Description” for detailed information.  
• Bit 2 – N: Negative Flag  
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the  
“Instruction Set Description” for detailed information.  
• Bit 1 – Z: Zero Flag  
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction  
Set Description” for detailed information.  
• Bit 0 – C: Carry Flag  
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set  
Description” for detailed information.  
9
8159C–AVR–07/09