ATmega64A
Figure 15-1. 16-bit Timer/Counter Block Diagram(1)
Count
TOVx
(Int.Req.)
Clear
Control Logic
Clock Select
Direction
TCLK
Edge
Detector
Tx
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTx
=
= 0
OCFxA
(Int.Req.)
Waveform
Generation
OCxA
OCxB
OCxC
=
OCRxA
OCFxB
(Int.Req.)
Fixed
TOP
Values
Waveform
Generation
=
OCRxB
OCFxC
(Int.Req.)
Waveform
Generation
=
OCRxC
( From Analog
Comparator Ouput )
ICFx (Int.Req.)
Edge
Detector
Noise
Canceler
ICRx
ICPx
TCCRxA
TCCRxB
TCCRxC
Note:
1. Refer to Figure 1-1 on page 2, Table 13-6 on page 76, and Table 13-15 on page 83 for
Timer/Counter1 and 3 pin placement and description.
15.2.1
Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-
ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 114. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the
Timer Interrupt Flag Register (TIFR) and Extended Timer Interrupt Flag Register (ETIFR). All
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK) and Extended
Timer Interrupt Mask Register (ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure
since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk ).
n
T
112
8160C–AVR–07/09
ATMEL [ ATMEL ]
