ATmega64A
14.11 Register Description
14.11.1 TCCR0 – Timer/Counter Control Register
Bit
7
FOC0
W
6
WGM00
R/W
0
5
COM01
R/W
0
4
COM00
R/W
0
3
WGM01
R/W
0
2
CS02
R/W
0
1
0
0x33 (0x53)
Read/Write
Initial Value
CS01
R/W
0
CS00
R/W
0
TCCR0
0
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR0 is written when
operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare
Match is forced on the waveform generation unit. The OC0 output is changed according to its
COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the
value present in the COM01:0 bits that determines the effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See Table 14-2 and “Modes of Operation”
on page 97.
Table 14-2. Waveform Generation Mode Bit Description(1)
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter Mode of
Operation
Update of
OCR0 at
TOV0 Flag
Set on
Mode
TOP
0
1
2
3
0
0
1
1
0
1
0
1
Normal
0xFF
0xFF
OCR0
0xFF
Immediate
TOP
MAX
PWM, Phase Correct
CTC
BOTTOM
MAX
Immediate
BOTTOM
Fast PWM
MAX
Note:
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set
in order to enable the output driver.
106
8160C–AVR–07/09
ATMEL [ ATMEL ]
