ATmega48PA/88PA/168PA/328P
0x3C01
0x3C02
out
ldi
SPH,r16
; Set Stack Pointer to top of RAM
r16,low(RAMEND)
SPL,r16
0x3C03
0x3C04
out
sei
; Enable interrupts
0x3C05
<instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega328P is:
Address Labels Code
Comments
;
.org 0x3C00
0x3C00
0x3C02
0x3C04
...
jmp
jmp
jmp
...
jmp
RESET
; Reset handler
EXT_INT0
EXT_INT1
...
; IRQ0 Handler
; IRQ1 Handler
;
0x3C32
;
SPM_RDY
; Store Program Memory Ready Handler
0x3C33 RESET: ldi
r16,high(RAMEND); Main program start
0x3C34
0x3C35
out
ldi
SPH,r16
; Set Stack Pointer to top of RAM
r16,low(RAMEND)
SPL,r16
0x3C36
0x3C37
out
sei
; Enable interrupts
0x3C38
<instr> xxx
11.5 Register Description
11.5.1
Moving Interrupts Between Application and Boot Space, ATmega88PA, ATmega168PA and ATmega328P
The MCU Control Register controls the placement of the Interrupt Vector table.
11.5.2
MCUCR – MCU Control Register
Bit
7
–
6
BODS
R
5
4
3
–
2
–
1
IVSEL
R/W
0
0
IVCE
R/W
0
0x35 (0x55)
Read/Write
Initial Value
BODSE
PUD
R/W
0
MCUCR
R
0
R
0
R
0
R
0
0
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section ”Boot Loader Support – Read-While-Write
Self-Programming, ATmega88PA, ATmega168PA and ATmega328P” on page 277 for details.
To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be fol-
lowed to change the IVSEL bit:
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
68
8161D–AVR–10/09
ATMEL [ ATMEL ]
