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ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
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ATmega48PA/88PA/168PA/328P  
Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and  
WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for  
keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System  
Reset Mode, WDIE must be set after each interrupt. This should however not be done within the  
interrupt service routine itself, as this might compromise the safety-function of the Watchdog  
System Reset mode. If the interrupt is not executed before the next time-out, a System Reset  
will be applied.  
Table 10-1. Watchdog Timer Configuration  
WDTON(1)  
WDE  
WDIE  
Mode  
Action on Time-out  
None  
1
1
1
0
0
1
0
1
0
Stopped  
Interrupt Mode  
System Reset Mode  
Interrupt  
Reset  
Interrupt and System Reset  
Mode  
Interrupt, then go to System  
Reset Mode  
1
0
1
x
1
x
System Reset Mode  
Reset  
Note:  
1. WDTON Fuse set to “0” means programmed and “1” means unprogrammed.  
• Bit 4 - WDCE: Watchdog Change Enable  
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,  
and/or change the prescaler bits, WDCE must be set.  
Once written to one, hardware will clear WDCE after four clock cycles.  
• Bit 3 - WDE: Watchdog System Reset Enable  
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is  
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-  
ditions causing failure, and a safe start-up after the failure.  
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0  
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-  
ning. The different prescaling values and their corresponding time-out periods are shown in  
Table 10-2 on page 55.  
Table 10-2. Watchdog Timer Prescale Select  
Number of WDT Oscillator  
Cycles  
Typical Time-out at  
VCC = 5.0V  
WDP3  
WDP2  
WDP1  
WDP0  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
2K (2048) cycles  
4K (4096) cycles  
16 ms  
32 ms  
64 ms  
0.125 s  
0.25 s  
0.5 s  
8K (8192) cycles  
16K (16384) cycles  
32K (32768) cycles  
64K (65536) cycles  
128K (131072) cycles  
1.0 s  
55  
8161D–AVR–10/09  
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