ATmega48PA/88PA/168PA/328P
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
10.8 Watchdog Timer
10.8.1
Features
• Clocked from separate On-chip Oscillator
• 3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
10.8.2
Overview
ATmega48PA/88PA/168PA/328P has an Enhanced Watchdog Timer (WDT). The WDT is a
timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a
system reset when the counter reaches a given time-out value. In normal operation mode, it is
required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the coun-
ter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or
system reset will be issued.
Figure 10-7. Watchdog Timer
128kHz
OSCILLATOR
WDP0
WDP1
WATCHDOG
WDP2
RESET
WDP3
WDE
MCU RESET
WDIF
INTERRUPT
WDIE
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
50
8161D–AVR–10/09
ATMEL [ ATMEL ]
