ATmega48PA/88PA/168PA/328P
28.6 SPI Timing Characteristics
See Figure 28-3 and Figure 28-4 for details.
Table 28-5. SPI Timing Parameters
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Min
Typ
Max
1
See Table 18-5
2
50% duty cycle
3
3.6
10
4
5
Hold
10
6
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low(1)
Rise/Fall time
Setup
0.5 • tsck
10
7
8
10
9
15
ns
10
11
12
13
14
15
16
17
18
Slave
4 • tck
2 • tck
Slave
Slave
1600
Slave
10
tck
Hold
Slave
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
Slave
15
10
Slave
20
20
Slave
Slave
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-
tion of other AVR microcontrollers manufactured in the same process technology. These
values are preliminary values representing design targets, and will be updated after character-
ization of actual silicon.
319
8161D–AVR–10/09
ATMEL [ ATMEL ]
