ATmega48PA/88PA/168PA/328P
Figure 27-1. Parallel Programming
+4.5 - 5.5V
+4.5 - 5.5V
RDY/BSY
OE
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC
AVCC
WR
BS1
PC[1:0]:PB[5:0]
DATA
XA0
XA1
PAGEL
+12 V
BS2
RESET
PC2
XTAL1
GND
Note:
VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V
Table 27-13. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O Function
0: Device is busy programming, 1: Device is
RDY/BSY
PD1
O
ready for new command
Output Enable (Active low)
Write Pulse (Active low)
OE
PD2
PD3
I
I
WR
Byte Select 1 (“0” selects Low byte, “1” selects
High byte)
BS1
PD4
I
XA0
XA1
PD5
PD6
I
I
XTAL Action Bit 0
XTAL Action Bit 1
Program memory and EEPROM Data Page
Load
PAGEL
PD7
I
I
Byte Select 2 (“0” selects Low byte, “1” selects
2’nd High byte)
BS2
PC2
DATA
{PC[1:0]: PB[5:0]}
I/O Bi-directional Data bus (Output when OE is low)
Table 27-14. Pin Values Used to Enter Programming Mode
Pin
PAGEL
XA1
Symbol
Value
Prog_enable[3]
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
0
0
0
0
XA0
BS1
300
8161D–AVR–10/09
ATMEL [ ATMEL ]
