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ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
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ATmega48PA/88PA/168PA/328P  
Table 26-5. Signature Row Addressing  
Signature Byte  
Z-Pointer Address  
0x0000  
Device Signature Byte 1  
Device Signature Byte 2  
Device Signature Byte 3  
RC Oscillator Calibration Byte  
0x0002  
0x0004  
0x0001  
Note:  
All other addresses are reserved for future use.  
26.8.11 Preventing Flash Corruption  
During periods of low VCC, the Flash program can be corrupted because the supply voltage is  
too low for the CPU and the Flash to operate properly. These issues are the same as for board  
level systems using the Flash, and the same design solutions should be applied.  
A Flash program corruption can be caused by two situations when the voltage is too low. First, a  
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,  
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions  
is too low.  
Flash corruption can easily be avoided by following these design recommendations (one is  
sufficient):  
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock  
bits to prevent any Boot Loader software updates.  
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.  
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-  
age matches the detection level. If not, an external low VCC reset protection circuit can be  
used. If a reset occurs while a write operation is in progress, the write operation will be  
completed provided that the power supply voltage is sufficient.  
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-  
vent the CPU from attempting to decode and execute instructions, effectively protecting  
the SPMCSR Register and thus the Flash from unintentional writes.  
26.8.12 Programming Time for Flash when Using SPM  
The calibrated RC Oscillator is used to time Flash accesses. Table 26-6 shows the typical pro-  
gramming time for Flash accesses from the CPU.  
Table 26-6. SPM Programming Time(1)  
Symbol  
Min Programming Time  
Max Programming Time  
Flash write (Page Erase, Page Write, and  
write Lock bits by SPM)  
3.7 ms  
4.5 ms  
Note:  
1. Minimum and maximum programming time is per individual operation.  
26.8.13 Simple Assembly Code Example for a Boot Loader  
;-the routine writes one page of data from RAM to Flash  
; the first data location in RAM is pointed to by the Y pointer  
; the first data location in Flash is pointed to by the Z-pointer  
;-error handling is not included  
286  
8161D–AVR–10/09  
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