欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48PA-AU的Datasheet PDF文件第202页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第203页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第204页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第205页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第207页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第208页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第209页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第210页  
ATmega48PA/88PA/168PA/328P  
Figure 20-1. UCPHAn and UCPOLn data transfer timing diagrams.  
UCPOL=0  
UCPOL=1  
XCK  
XCK  
Data setup (TXD)  
Data sample (RXD)  
Data setup (TXD)  
Data sample (RXD)  
XCK  
XCK  
Data setup (TXD)  
Data sample (RXD)  
Data setup (TXD)  
Data sample (RXD)  
20.5 Frame Formats  
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM  
mode has two valid frame formats:  
• 8-bit data with MSB first  
• 8-bit data with LSB first  
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of  
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete  
frame is transmitted, a new frame can directly follow it, or the communication line can be set to  
an idle (high) state.  
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The  
Receiver and Transmitter use the same setting. Note that changing the setting of any of these  
bits will corrupt all ongoing communication for both the Receiver and Transmitter.  
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit com-  
plete interrupt will then signal that the 16-bit value has been shifted out.  
20.5.1  
USART MSPIM Initialization  
The USART in MSPIM mode has to be initialized before any communication can take place. The  
initialization process normally consists of setting the baud rate, setting master mode of operation  
(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the  
Receiver. Only the transmitter can operate independently. For interrupt driven USART opera-  
tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when  
doing the initialization.  
Note:  
To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be  
zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the  
UBRRn must then be written to the desired value after the transmitter is enabled, but before the  
first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces-  
sary if the initialization is done immediately after a reset since UBRRn is reset to zero.  
Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that  
there is no ongoing transmissions during the period the registers are changed. The TXCn Flag  
can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can  
206  
8161D–AVR–10/09  
 复制成功!