ATmega16U4/ATmega32U4
2.1
Block Diagram
Figure 2-1. Block Diagram
PF7 - PF4
PF0
PC7
PC6
PF1
VCC
GND
PORTF DRIVERS
PORTC DRIVERS
DATA REGISTER
DATA DIR.
REG. PORTF
DATA REGISTER
DATA DIR.
REG. PORTC
PORTF
PORTC
8-BIT DA TA BUS
POR - BOD
RESET
INTERNAL
CALIB. OSC
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
COUNTER
STACK
POINTER
JTAG TAP
TIMING AND
CONTROL
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
TIMERS/
COUNTERS
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INTERRUPT
UNIT
UVcc
UCap
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
ON-CHIP
USB PAD 3V
REGULATOR
EEPROM
TEMPERATURE
SENSOR
CONTROL
LINES
ALU
1uF
PLL
AVCC
HIGH SPEED
TIMER/PWM
ADC
AGND
AREF
STATUS
REGISTER
VBUS
DP
USB 2.0
DM
ANALOG
TWO-WIRE SERIAL
INTERFACE
USART1
SPI
COMPARATOR
DATA REGISTER
DATA DIR.
REG. PORTE
DATA REGISTER
DATA DIR.
REG. PORTB
DATA REGISTER
DATA DIR.
REG. PORTD
PORTE
PORTB
PORTD
PORTB DRIVERS
PORTD DRIVERS
PORTE DRIVERS
PE2
PE6
PB7 - PB0
PD7 - PD0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega16U4/ATmega32U4 provides the following features: 16/32K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512Bytes/1K bytes EEPROM,
1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32
general purpose working registers, four flexible Timer/Counters with compare modes and PWM,
one more high-speed Timer/Counter with compare modes and PLL adjustable source, one
USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-
4
7766ES–AVR–04/10
ATMEL [ ATMEL ]
