ATmega16U4/ATmega32U4
2.1
Block Diagram
Block Diagram
Figure 2-1.
PF7 - PF4
PF1 PF0
PC7 PC6
VCC
GND
PORTF DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTC
8-BIT DA TA BUS
DATA DIR.
REG. PORTC
POR - BOD
RESET
INTERNAL
OSCILLATOR
CALIB. OSC
JTAG TAP
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
OSCILLATOR
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
TIMERS/
COUNTERS
INTERRUPT
UNIT
TIMING AND
CONTROL
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
RESET
XTAL1
XTAL2
UVcc
ON-CHIP
USB PAD 3V
REGULATOR
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
EEPROM
UCap
1uF
TEMPERATURE
SENSOR
AVCC
AGND
AREF
ADC
CONTROL
LINES
ALU
HIGH SPEED
STATUS
REGISTER
TIMER/PWM
PLL
VBUS
DP
USB 2.0
DM
TWO-WIRE SERIAL
INTERFACE
ANALOG
COMPARATOR
USART1
SPI
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PE6
PE2
PB7 - PB0
PD7 - PD0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega16U4/ATmega32U4 provides the following features: 16/32K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512Bytes/1K bytes EEPROM,
1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32
general purpose working registers, four flexible Timer/Counters with compare modes and PWM,
one more high-speed Timer/Counter with compare modes and PLL adjustable source, one
USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-
4
7766DS–AVR–01/09
ATMEL [ ATMEL CORPORATION ]
