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ATMEGA16U2 参数 Datasheet PDF下载

ATMEGA16U2图片预览
型号: ATMEGA16U2
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash和USB控制器8/16 / 32K字节 [8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller]
分类和应用: 微控制器
文件页数/大小: 21 页 / 341 K
品牌: ATMEL [ ATMEL CORPORATION ]
 浏览型号ATMEGA16U2的Datasheet PDF文件第7页浏览型号ATMEGA16U2的Datasheet PDF文件第8页浏览型号ATMEGA16U2的Datasheet PDF文件第9页浏览型号ATMEGA16U2的Datasheet PDF文件第10页浏览型号ATMEGA16U2的Datasheet PDF文件第12页浏览型号ATMEGA16U2的Datasheet PDF文件第13页浏览型号ATMEGA16U2的Datasheet PDF文件第14页浏览型号ATMEGA16U2的Datasheet PDF文件第15页  
ATmega8U2/16U2/32U2
7. Instruction Set Summary
Mnemonics
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
RJMP
IJMP
JMP
RCALL
ICALL
CALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
SBI
CBI
LSL
LSR
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
P,b
P,b
Rd
Rd
k
k
k
Operands
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd,K
Rd,K
Rd
Rd
Rd
Rd
Rd
BRANCH INSTRUCTIONS
k
Description
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Relative Jump
Indirect Jump to (Z)
Direct Jump
Relative Subroutine Call
Indirect Call to (Z)
Direct Subroutine Call
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Operation
Rd
Rd + Rr
Rd
Rd + Rr + C
Rdh:Rdl
Rdh:Rdl + K
Rd
Rd - Rr
Rd
Rd - K
Rd
Rd - Rr - C
Rd
Rd - K - C
Rdh:Rdl
Rdh:Rdl - K
Rd
Rd
Rr
Rd
Rd
K
Rd
Rd v Rr
Rd
Rd v K
Rd
Rd
Rr
Rd
0xFF
Rd
Rd
0x00
Rd
Rd
Rd v K
Rd
Rd
(0xFF - K)
Rd
Rd + 1
Rd
Rd
1
Rd
Rd
Rd
Rd
Rd
Rd
Rd
0xFF
PC
PC + k + 1
PC
Z
PC
k
PC
PC + k + 1
PC
Z
PC
k
PC
STACK
PC
STACK
if (Rd = Rr) PC
PC + 2 or 3
Rd
Rr
Rd
Rr
C
Rd
K
if (Rr(b)=0) PC
PC + 2 or 3
if (Rr(b)=1) PC
PC + 2 or 3
if (P(b)=0) PC
PC + 2 or 3
if (P(b)=1) PC
PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC
PC + k + 1
if (Z = 0) then PC
PC + k + 1
if (C = 1) then PC
PC + k + 1
if (C = 0) then PC
PC + k + 1
if (C = 0) then PC
PC + k + 1
if (C = 1) then PC
PC + k + 1
if (N = 1) then PC
PC + k + 1
if (N = 0) then PC
PC + k + 1
if (N
V= 0) then PC
PC + k + 1
if (N
V= 1) then PC
PC + k + 1
if (H = 1) then PC
PC + k + 1
if (H = 0) then PC
PC + k + 1
if (T = 1) then PC
PC + k + 1
if (T = 0) then PC
PC + k + 1
if (V = 1) then PC
PC + k + 1
if (V = 0) then PC
PC + k + 1
if ( I = 1) then PC
PC + k + 1
if ( I = 0) then PC
PC + k + 1
I/O(P,b)
1
I/O(P,b)
0
Rd(n+1)
Rd(n), Rd(0)
0
Rd(n)
Rd(n+1), Rd(7)
0
Flags
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
#Clocks
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
4
4
5
5
5
1/2/3
1
1
1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2
2
1
1
ARITHMETIC AND LOGIC INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
11
7799CS–AVR–12/09