ATMEGA16M1_09 参数 Datasheet PDF下载

ATmega16M1/32M1/64M1

Address

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Name

GPIOR2

GPIOR1

Reserved

Reserved

TIFR1

TIFR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

PORTE

DDRE

PINE

PORTD

DDRD

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

Reserved

Reserved

Reserved

Bit 7

GPIOR27

GPIOR17

–

–

–

–

–

–

–

–

–

–

–

–

–

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

–

–

–

Bit 6

GPIOR26

GPIOR16

–

–

–

–

–

–

–

–

–

–

–

–

–

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

–

–

Bit 5

GPIOR25

GPIOR15

–

–

ICF1

–

–

–

–

–

–

–

–

–

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

–

–

Bit 4

GPIOR24

GPIOR14

–

–

–

–

–

–

–

–

–

–

–

–

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

–

–

Bit 3

GPIOR23

GPIOR13

–

–

–

–

–

–

–

–

–

–

–

–

–

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

–

–

Bit 2

GPIOR22

GPIOR12

–

–

OCF1B

OCF0B

–

–

–

–

–

–

PORTE2

DDE2

PINE2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

–

–

Bit 1

GPIOR21

GPIOR11

–

–

OCF1A

OCF0A

–

–

–

–

–

–

PORTE1

DDE1

PINE1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

–

–

Bit 0

GPIOR20

GPIOR10

–

–

TOV1

TOV0

–

–

–

–

–

–

PORTE0

DDE0

PINE0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

–

–

Page

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca-

tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are

reserved.

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8209BS–AVR–10/09