欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第76页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第77页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第78页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第79页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第81页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第82页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第83页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第84页  
AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis-  
connected from the port, and becomes the input of the inverting Oscillator amplifier. In this  
mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin.  
PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.  
If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.  
• SCK/PCINT5 – Port B, Bit 5  
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a  
Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is  
enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced  
by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.  
PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.  
• MISO/PCINT4 – Port B, Bit 4  
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a  
Master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is  
enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced  
by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.  
PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source.  
• MOSI/OC2/PCINT3 – Port B, Bit 3  
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a  
Slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is  
enabled as a Master, the data direction of this pin is controlled by DDB3. When the pin is forced  
by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit.  
OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the  
Timer/Counter2 Compare Match. The PB3 pin has to be configured as an output (DDB3 set  
(one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer  
function.  
PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source.  
• SS/OC1B/PCINT2 – Port B, Bit 2  
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input  
regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin is driven low.  
When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When  
the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.  
OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the  
Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set  
(one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer  
function.  
PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source.  
• OC1A/PCINT1 – Port B, Bit 1  
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the  
Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set  
80  
ATmega48/88/168  
2545M–AVR–09/07