UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new inter-
rupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Reg-
ister has been shifted out and there are no new data currently present in the transmit buffer. The
TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be
cleared by writing a one to its bit location. The TXC Flag is useful in half-duplex communication
interfaces (like the RS485 standard), where a transmitting application must enter Receive mode
and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit
Complete Interrupt will be executed when the TXC Flag becomes set (provided that global inter-
rupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine
does not have to clear the TXC Flag, this is done automatically when the interrupt is executed.
Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPM1 = 1), the Transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
Disabling the
Transmitter
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed (i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted). When disabled, the Transmitter
will no longer override the TxD pin.
142
ATmega8(L)
2486T–AVR–05/08
ATMEL [ ATMEL ]
