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ATMEGA48V-10MMHR 参数 Datasheet PDF下载

ATMEGA48V-10MMHR图片预览
型号: ATMEGA48V-10MMHR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQCC28, 4 X 4 MM, 1 MM HEIGHT, 0.45 MM PITCH, GREEN, PLASTIC, VQFN-28]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第77页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第78页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第79页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第80页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第82页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第83页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第84页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第85页  
ATmega48/88/168  
(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer  
function.  
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.  
• ICP1/CLKO/PCINT0 – Port B, Bit 0  
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.  
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The  
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the  
PORTB0 and DDB0 settings. It will also be output during reset.  
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.  
Table 13-4 and Table 13-5 relate the alternate functions of Port B to the overriding signals  
shown in Figure 13-5 on page 77. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the  
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.  
Table 13-4. Overriding Signals for Alternate Functions in PB7..PB4  
Signal  
Name  
PB7/XTAL2/  
PB6/XTAL1/  
PB5/SCK/  
PCINT5  
PB4/MISO/  
PCINT4  
TOSC2/PCINT7(1)  
TOSC1/PCINT6(1)  
INTRC • EXTCK+  
AS2  
PUOE  
PUOV  
DDOE  
INTRC + AS2  
0
SPE • MSTR  
PORTB5 • PUD  
SPE • MSTR  
SPE • MSTR  
PORTB4 • PUD  
SPE • MSTR  
0
INTRC • EXTCK+  
AS2  
INTRC + AS2  
DDOV  
PVOE  
0
0
0
0
0
0
SPE • MSTR  
SPE • MSTR  
SPI SLAVE  
OUTPUT  
PVOV  
0
0
SCK OUTPUT  
PCINT5 • PCIE0  
1
INTRC • EXTCK +  
AS2 + PCINT7 •  
PCIE0  
INTRC + AS2 +  
PCINT6 • PCIE0  
DIEOE  
PCINT4 • PCIE0  
1
(INTRC + EXTCK) •  
AS2  
DIEOV  
DI  
INTRC • AS2  
PCINT5 INPUT  
SCK INPUT  
PCINT4 INPUT  
PCINT7 INPUT  
Oscillator Output  
PCINT6 INPUT  
SPI MSTR INPUT  
Oscillator/Clock  
Input  
AIO  
81  
2545M–AVR–09/07