ATmega8(L)
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 15 on page 38. The POR is activated whenever VCC is below the detection
level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in
supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 15. MCU Start-up, RESET Tied to VCC
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 16. MCU Start-up, RESET Extended Externally
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
39
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
