ATmega8(L)
Figure 111. Parallel Programming Timing, Reading Sequence (within the same Page) with Tim-
ing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
BS1
tBVDV
tOLDV
OE
tOHDZ
ADDR1 (Low Byte)
DATA (High Byte)
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 109 on page 227 (that is, tDVXH, tXHXL, and tXLDX
)
also apply to reading operation
Table 95. Parallel Programming Characteristics, VCC = 5V 10ꢀ
Symbol
VPP
Parameter
Min
Typ
Max
12.5
250
Units
V
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
11.5
IPP
A
tDVXH
tXLXH
tXHXL
tXLDX
tXLWL
tXLPH
tPLXH
tBVPH
tPHPL
tPLBX
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
67
200
150
67
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
0
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
0
150
67
ns
150
67
67
67
BS1 Valid to WR Low
67
WR Pulse Width Low
150
0
WR Low to RDY/BSY Low
WR Low to RDY/BSY High(1)
WR Low to RDY/BSY High for Chip Erase(2)
1
4.5
9
s
3.7
7.5
ms
228
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
