ATmega8(L)
Performing Page
Erase by SPM
To execute page erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
•
•
Page Erase to the RWW section: The NRWW section can be read during the page erase
Page Erase to the NRWW section: The CPU is halted during the operation
Note: If an interrupt occurs in the timed sequence, the four cycle access cannot be guaranteed.
In order to ensure atomic operation, disable interrupts before writing to SPMCSR.
Filling the Temporary
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
Buffer (Page Loading) “00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The con-
tent of PCWORD in the Z-register is used to address the data in the temporary page buffer. The
temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in
SPMCR. It is also erased after a System Reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
Note:
If the EEPROM is written in the middle of an SPM page Load operation, all data loaded will be lost
Performing a Page
Write
To execute page write, set up the address in the Z-pointer, write “X0000101” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
•
•
Page Write to the RWW section: The NRWW section can be read during the page write
Page Write to the NRWW section: The CPU is halted during the operation
Using the SPM
Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling
the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be
moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in “Interrupts” on page 46.
Consideration While
Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
Prevent Reading the
RWW Section During
Self-Programming
During Self-Programming (either page erase or page write), the RWW section is always blocked
for reading. The user software itself must prevent that this section is addressed during the self
programming operation. The RWWSB in the SPMCR will be set as long as the RWW section is
busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as
described in “Interrupts” on page 46, or the interrupts must be disabled. Before addressing the
RWW section after the programming is completed, the user software must clear the RWWSB by
writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 212 for
an example.
Setting the Boot
Loader Lock Bits by
SPM
To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are
the Boot Lock Bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
Bit
7
6
5
4
3
2
1
0
R0
1
1
BLB12
BLB11
BLB02
BLB01
1
1
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2486AA–AVR–02/2013
ATMEL [ ATMEL ]
