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ATMEGA8L-8MUR 参数 Datasheet PDF下载

ATMEGA8L-8MUR图片预览
型号: ATMEGA8L-8MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位爱特梅尔带有8K字节的系统内可编程闪存 [8-bit Atmel with 8KBytes In-System PRogrammable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路异步传输模式PCATM时钟
文件页数/大小: 331 页 / 6705 K
品牌: ATMEL [ ATMEL ]
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ATmega8(L)  
The X-register, Y-  
The registers R26..R31 have some added functions to their general purpose usage. These reg-  
register and Z-register isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect  
address registers X, Y and Z are defined as described in Figure 4.  
Figure 4. The X-register, Y-register and Z-Register  
15  
XH  
YH  
XL  
0
0
X-register  
7
0
0
7
R27 (0x1B)  
R26 (0x1A)  
15  
YL  
ZL  
0
0
Y-register  
Z-register  
7
7
R29 (0x1D)  
R28 (0x1C)  
15  
ZH  
0
0
7
7
0
R31 (0x1F)  
R30 (0x1E)  
In the different addressing modes these address registers have functions as fixed displacement,  
automatic increment, and automatic decrement (see the Instruction Set Reference for details).  
Stack Pointer  
The Stack is mainly used for storing temporary data, for storing local variables and for storing  
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points  
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-  
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack  
Pointer.  
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt  
Stacks are located. This Stack space in the data SRAM must be defined by the program before  
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to  
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack  
with the PUSH instruction, and it is decremented by two when the return address is pushed onto  
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is  
popped from the Stack with the POP instruction, and it is incremented by two when address is  
popped from the Stack with return from subroutine RET or return from interrupt RETI.  
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of  
bits actually used is implementation dependent. Note that the data space in some implementa-  
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register  
will not be present.  
Bit  
15  
SP15  
SP7  
7
14  
SP14  
SP6  
6
13  
SP13  
SP5  
5
12  
SP12  
SP4  
4
11  
SP11  
SP3  
3
10  
SP10  
SP2  
2
9
SP9  
SP1  
1
8
SP8  
SP0  
0
SPH  
SPL  
Read/Write  
Initial Value  
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
R/W  
R/W  
0
0
0
0
0
0
0
0
0
Instruction  
Execution Timing  
This section describes the general access timing concepts for instruction execution. The  
Atmel®AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected clock  
source for the chip. No internal clock division is used.  
13  
2486AA–AVR–02/2013