ATmega8(L)
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 31. Prescaler for Timer/Counter0 and Timer/Counter1(1)
clkI/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. The synchronization logic on the input pins (T1/T0) is shown in Figure 30 on page 73
Special Function IO
Register – SFIOR
Bit
7
–
6
–
5
–
4
–
3
ACME
R/W
0
2
1
PSR2
R/W
0
0
PSR10
R/W
0
PUD
R/W
0
SFIOR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset.
The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will
have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a
reset of this prescaler will affect both timers. This bit will always be read as zero.
74
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
