Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
PORTG
DDRG
PING
-
-
PORTG5
DDG5
PORTG4
DDG4
PORTG3
DDG3
PORTG2
DDG2
PORTG1
DDG1
PORTG0
DDG0
page 98
page 98
page 98
page 97
page 98
page 98
page 97
page 97
page 98
page 97
page 97
page 97
page 97
page 97
page 97
page 96
page 96
page 96
page 96
page 96
page 96
-
-
-
-
PING5
PORTF5
DDF5
PING4
PORTF4
DDF4
PING3
PORTF3
DDF3
PING2
PORTF2
DDF2
PING1
PORTF1
DDF1
PING0
PORTF0
DDF0
PORTF
DDRF
PINF
PORTF7
DDF7
PORTF6
DDF6
PINF6
PORTE6
DDE6
PINE6
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
PORTA6
DDA6
PINA6
PINF7
PORTE7
DDE7
PINE7
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
PORTA7
DDA7
PINA7
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
PORTE
DDRE
PINE
PORTE5
DDE5
PORTE4
DDE4
PORTE3
DDE3
PORTE2
DDE2
PORTE1
DDE1
PORTE0
DDE0
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
PORTD
DDRD
PIND
PORTD5
DDD5
PORTD4
DDD4
PORTD3
DDD3
PORTD2
DDD2
PORTD1
DDD1
PORTD0
DDD0
PIND5
PORTC5
DDC5
PIND4
PORTC4
DDC4
PIND3
PORTC3
DDC3
PIND2
PORTC2
DDC2
PIND1
PORTC1
DDC1
PIND0
PORTC0
DDC0
PORTC
DDRC
PINC
PINC5
PORTB5
DDB5
PINC4
PORTB4
DDB4
PINC3
PORTB3
DDB3
PINC2
PORTB2
DDB2
PINC1
PORTB1
DDB1
PINC0
PORTB0
DDB0
PORTB
DDRB
PINB
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
PORTA
DDRA
PINA
PORTA5
DDA5
PORTA4
DDA4
PORTA3
DDA3
PORTA2
DDA2
PORTA1
DDA1
PORTA0
DDA0
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-
ters as data space using LD and ST instructions, $20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the
64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
15
2549QS–AVR–02/2014