ATmega48/88/168
8-bit Timer/Counter
Register Description
Timer/Counter Control
Register A – TCCR2A
Bit
7
COM2A1
R/W
6
COM2A0
R/W
5
COM2B1
R/W
4
COM2B0
R/W
3
–
2
–
1
WGM21
R/W
0
0
WGM20
R/W
0
TCCR2A
Read/Write
Initial Value
R
0
R
0
0
0
0
0
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the
COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-
responding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 60 shows the COM2A1:0 bit functionality when the
WGM22:0 bits are set to a normal or CTC mode (non-PWM).
Table 60. Compare Output Mode, non-PWM Mode
COM2A1
COM2A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Toggle OC2A on Compare Match
Clear OC2A on Compare Match
Set OC2A on Compare Match
Table 61 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast
PWM mode.
Table 61. Compare Output Mode, Fast PWM Mode(1)
COM2A1
COM2A0
Description
0
0
0
1
Normal port operation, OC2A disconnected.
WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1
1
0
1
Clear OC2A on Compare Match, set OC2A at TOP
Set OC2A on Compare Match, clear OC2A at TOP
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 138 for more details.
Table 62 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to
phase correct PWM mode.
143
2545D–AVR–07/04
ATMEL [ ATMEL ]
