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ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
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Frame Formats  
A serial frame is defined to be one character of data bits with synchronization bits (start  
and stop bits), and optionally a parity bit for error checking. The USART accepts all 30  
combinations of the following as valid frame formats:  
1 start bit  
5, 6, 7, 8, or 9 data bits  
no, even or odd parity bit  
1 or 2 stop bits  
A frame starts with the start bit followed by the least significant data bit. Then the next  
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If  
enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-  
plete frame is transmitted, it can be directly followed by a new frame, or the  
communication line can be set to an idle (high) state. Figure 73 illustrates the possible  
combinations of the frame formats. Bits inside brackets are optional.  
Figure 73. Frame Formats  
FRAME  
(IDLE)  
St  
0
1
2
3
4
[5]  
[6]  
[7]  
[8]  
[P] Sp1 [Sp2] (St / IDLE)  
St  
(n)  
P
Start bit, always low.  
Data bits (0 to 8).  
Parity bit. Can be odd or even.  
Stop bit, always high.  
Sp  
IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be  
high.  
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn  
bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.  
Note that changing the setting of any of these bits will corrupt all ongoing communica-  
tion for both the Receiver and Transmitter.  
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame.  
The USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selec-  
tion between one or two stop bits is done by the USART Stop Bit Select (USBSn) bit.  
The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be  
detected in the cases where the first stop bit is zero.  
Parity Bit Calculation  
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is  
used, the result of the exclusive or is inverted. The relation between the parity bit and  
data bits is as follows:  
P
P
= d  
= d  
⊕ … ⊕ d d d d 0  
3 2 1 0  
even  
n 1  
n 1  
⊕ … ⊕ d d d d 1  
odd  
3 2 1 0  
Peven Parity bit using even parity  
Podd  
dn  
Parity bit using odd parity  
Data bit n of the character  
166  
ATmega48/88/168  
2545D–AVR–07/04  
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