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ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
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ATmega48/88/168  
Asynchronous operation  
of the Timer/Counter  
Asynchronous Operation of  
Timer/Counter2  
When Timer/Counter2 operates asynchronously, some considerations must be taken.  
Warning: When switching between asynchronous and synchronous clocking of  
Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be  
corrupted. A safe procedure for switching clock source is:  
1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.  
2. Select clock source by setting AS2 as appropriate.  
3. Write new values to TCNT2, OCR2x, and TCCR2x.  
4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and  
TCR2xUB.  
5. Clear the Timer/Counter2 Interrupt Flags.  
6. Enable interrupts, if needed.  
The CPU main clock frequency must be more than four times the Oscillator  
frequency.  
When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is  
transferred to a temporary register, and latched after two positive edges on TOSC1.  
The user should not write a new value before the contents of the temporary register  
have been transferred to its destination. Each of the five mentioned registers have  
their individual temporary register, which means that e.g. writing to TCNT2 does not  
disturb an OCR2x write in progress. To detect that a transfer to the destination  
register has taken place, the Asynchronous Status Register – ASSR has been  
implemented.  
When entering Power-save or ADC Noise Reduction mode after having written to  
TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been  
updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will  
enter sleep mode before the changes are effective. This is particularly important if  
any of the Output Compare2 interrupt is used to wake up the device, since the  
Output Compare function is disabled during writing to OCR2x or TCNT2. If the write  
cycle is not finished, and the MCU enters sleep mode before the corresponding  
OCR2xUB bit returns to zero, the device will never receive a compare match  
interrupt, and the MCU will not wake up.  
If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise  
Reduction mode, precautions must be taken if the user wants to re-enter one of  
these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time  
between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the  
interrupt will not occur, and the device will fail to wake up. If the user is in doubt  
whether the time before re-entering Power-save or ADC Noise Reduction mode is  
sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has  
elapsed:  
1. Write a value to TCCR2x, TCNT2, or OCR2x.  
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.  
3. Enter Power-save or ADC Noise Reduction mode.  
When the asynchronous operation is selected, the 32.768 kHz Oscillator for  
Timer/Counter2 is always running, except in Power-down and Standby modes. After  
a Power-up Reset or wake-up from Power-down or Standby mode, the user should  
be aware of the fact that this Oscillator might take as long as one second to stabilize.  
The user is advised to wait for at least one second before using Timer/Counter2  
after power-up or wake-up from Power-down or Standby mode. The contents of all  
149  
2545D–AVR–07/04  
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