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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第59页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第60页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第61页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第62页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第64页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第65页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第66页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第67页  
ATmega32(L)  
• OC1A – Port D, Bit 5  
OC1A, Output Compare Match A output: The PD5 pin can serve as an external output  
for the Timer/Counter1 Output Compare A. The pin has to be configured as an output  
(DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the  
PWM mode timer function.  
• OC1B – Port D, Bit 4  
OC1B, Output Compare Match B output: The PD4 pin can serve as an external output  
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output  
(DDD4 set (one)) to serve this function. The OC1B pin is also the output pin for the  
PWM mode timer function.  
• INT1 – Port D, Bit 3  
INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt  
source.  
• INT0 – Port D, Bit 2  
INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt  
source.  
• TXD – Port D, Bit 1  
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is  
enabled, this pin is configured as an output regardless of the value of DDD1.  
• RXD – Port D, Bit 0  
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is  
enabled this pin is configured as an input regardless of the value of DDD0. When the  
USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0  
bit.  
Table 32 and Table 33 relate the alternate functions of Port D to the overriding signals  
shown in Figure 26 on page 54.  
Table 32. Overriding Signals for Alternate Functions PD7..PD4  
Signal Name  
PUOE  
PUOV  
DDOE  
DDOV  
PVOE  
PVOV  
DIEOE  
DIEOV  
DI  
PD7/OC2  
PD6/ICP1  
PD5/OC1A  
PD4/OC1B  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OC2 ENABLE  
0
OC1A ENABLE  
OC1B ENABLE  
OC2  
0
OC1A  
OC1B  
0
0
0
0
0
0
0
0
ICP1 INPUT  
AIO  
63  
2503J–AVR–10/06  
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