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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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ATmega32(L)  
I/O Ports  
Introduction  
All AVR ports have true Read-Modify-Write functionality when used as general digital  
I/O ports. This means that the direction of one port pin can be changed without uninten-  
tionally changing the direction of any other pin with the SBI and CBI instructions. The  
same applies when changing drive value (if configured as output) or enabling/disabling  
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive  
characteristics with both high sink and source capability. The pin driver is strong enough  
to drive LED displays directly. All port pins have individually selectable pull-up resistors  
with a supply-voltage invariant resistance. All I/O pins have protection diodes to both  
V
CC and Ground as indicated in Figure 22. Refer to “Electrical Characteristics” on page  
287 for a complete list of parameters.  
Figure 22. I/O Pin Equivalent Schematic  
Rpu  
Pxn  
Logic  
Cpin  
See Figure 23  
"General Digital I/O" for  
Details  
All registers and bit references in this section are written in general form. A lower case  
“x” represents the numbering letter for the port, and a lower case “n” represents the bit  
number. However, when using the register or bit defines in a program, the precise form  
must be used. i.e., PORTB3 for bit no. 3 in Port B, here documented generally as  
PORTxn. The physical I/O Registers and bit locations are listed in “Register Description  
for I/O Ports” on page 64.  
Three I/O memory address locations are allocated for each port, one each for the Data  
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The  
Port Input Pins I/O location is read only, while the Data Register and the Data Direction  
Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables the  
pull-up function for all pins in all ports when set.  
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on  
page 50. Most port pins are multiplexed with alternate functions for the peripheral fea-  
tures on the device. How each alternate function interferes with the port pin is described  
in “Alternate Port Functions” on page 54. Refer to the individual module sections for a  
full description of the alternate functions.  
Note that enabling the alternate function of some of the port pins does not affect the use  
of the other pins in the port as general digital I/O.  
49  
2503J–AVR–10/06  
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