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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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ATmega32(L)  
Overview of the TWI  
Module  
The TWI module is comprised of several submodules, as shown in Figure 84. All regis-  
ters drawn in a thick line are accessible through the AVR data bus.  
Figure 84. Overview of the TWI Module  
SCL  
SDA  
Spike  
Filter  
Spike  
Filter  
Slew-rate  
Control  
Slew-rate  
Control  
Bus Interface Unit  
Bit Rate Generator  
START / STOP  
Spike Suppression  
Prescaler  
Control  
Address/Data Shift  
Register (TWDR)  
Bit Rate Register  
(TWBR)  
Arbitration detection  
Ack  
Address Match Unit  
Control Unit  
Address Register  
(TWAR)  
Status Register  
(TWSR)  
Control Register  
(TWCR)  
TWI Unit  
State Machine and  
Status control  
Address Comparator  
SCL and SDA Pins  
These pins interface the AVR TWI with the rest of the MCU system. The output drivers  
contain a slew-rate limiter in order to conform to the TWI specification. The input stages  
contain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-  
nal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to  
the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in  
some systems eliminate the need for external ones.  
Bit Rate Generator Unit  
This unit controls the period of SCL when operating in a Master mode. The SCL period  
is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in  
the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-  
caler settings, but the CPU clock frequency in the slave must be at least 16 times higher  
than the SCL frequency. Note that slaves may prolong the SCL low period, thereby  
reducing the average TWI bus clock period. The SCL frequency is generated according  
to the following equation:  
CPU Clock frequency  
SCL frequency = -----------------------------------------------------------  
TWPS  
16 + 2(TWBR) 4  
TWBR = Value of the TWI Bit Rate Register  
TWPS = Value of the prescaler bits in the TWI Status Register  
Note:  
Pull-up resistor values should be selected according to the SCL frequency and the  
capacitive bus line load. See Table 119 on page 290 for value of pull-up resistor.  
175  
2503J–AVR–10/06  
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