ATmega32(L)
The EEPROM Address
Register – EEARH and EEARL
Bit
15
14
13
12
11
10
9
EEAR9
EEAR1
1
8
EEAR8
EEAR0
0
–
–
–
–
–
–
EEARH
EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
7
R
6
R
5
R
4
R
3
R
2
R
Read/Write
Initial Value
R/W
R/W
0
R/W
R/W
X
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
X
X
X
X
X
X
X
X
• Bits 15..10 – Res: Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bits 9..0 – EEAR9..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address
in the 1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 1023. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
The EEPROM Data Register –
EEDR
Bit
7
6
5
4
3
2
1
0
MSB
R/W
0
LSB
R/W
0
EEDR
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-
ation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
The EEPROM Control Register
– EECR
Bit
7
–
6
–
5
–
4
–
3
EERIE
R/W
0
2
EEMWE
R/W
0
1
EEWE
R/W
X
0
EERE
R/W
0
EECR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is set, setting EEWE within four clock cycles will write data to the
EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.
19
2503J–AVR–10/06
ATMEL [ ATMEL ]
