ATmega16(L)
The receive function example reads all the I/O registers into the register file before any
computation is done. This gives an optimal receive buffer utilization since the buffer
location read will be free to accept new data as early as possible.
Receive Compete Flag and
Interrupt
The USART Receiver has one flag that indicates the receiver state.
The Receive Complete (RXC) flag indicates if there are unread data present in the
receive buffer. This flag is one when unread data exist in the receive buffer, and zero
when the receive buffer is empty (i.e., does not contain any unread data). If the receiver
is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit
will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART
Receive Complete Interrupt will be executed as long as the RXC flag is set (provided
that global interrupts are enabled). When interrupt-driven data reception is used, the
receive complete routine must read the received data from UDR in order to clear the
RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates.
Receiver Error Flags
The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and
Parity Error (PE). All can be accessed by reading UCSRA. Common for the error flags is
that they are located in the receive buffer together with the frame for which they indicate
the error status. Due to the buffering of the error flags, the UCSRA must be read before
the receive buffer (UDR), since reading the UDR I/O location changes the buffer read
location. Another equality for the error flags is that they can not be altered by software
doing a write to the flag location. However, all flags must be set to zero when the
UCSRA is written for upward compatibility of future USART implementations. None of
the error flags can generate interrupts.
The Frame Error (FE) flag indicates the state of the first stop bit of the next readable
frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly
read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This
flag can be used for detecting out-of-sync conditions, detecting break conditions and
protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC
since the receiver ignores all, except for the first, stop bits. For compatibility with future
devices, always set this bit to zero when writing to UCSRA.
The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition.
A Data OverRun occurs when the receive buffer is full (two characters), it is a new char-
acter waiting in the receive Shift Register, and a new start bit is detected. If the DOR flag
is set there was one or more serial frame lost between the frame last read from UDR,
and the next frame read from UDR. For compatibility with future devices, always write
this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame
received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (PE) flag indicates that the next frame in the receive buffer had a parity
error when received. If parity check is not enabled the PE bit will always be read zero.
For compatibility with future devices, always set this bit to zero when writing to UCSRA.
For more details see “Parity Bit Calculation” on page 142 and “Parity Checker” on page
149.
Parity Checker
The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type
of parity check to be performed (odd or even) is selected by the UPM0 bit. When
enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit from the serial frame. The result of the check is
stored in the receive buffer together with the received data and stop bits. The Parity
Error (PE) flag can then be read by software to check if the frame had a parity error.
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ATMEL [ ATMEL ]
