either write new data to UDR in order to clear UDRE or disable the Data Register empty
Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) flag bit is set one when the entire frame in the transmit
Shift Register has been shifted out and there are no new data currently present in the
transmit buffer. The TXC flag bit is automatically cleared when a transmit complete
interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC
flag is useful in half-duplex communication interfaces (like the RS485 standard), where
a transmitting application must enter receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART
Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided
that global interrupts are enabled). When the transmit complete interrupt is used, the
interrupt handling routine does not have to clear the TXC flag, this is done automatically
when the interrupt is executed.
Parity Generator
The parity generator calculates the parity bit for the serial frame data. When parity bit is
enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
Disabling the Transmitter
The disabling of the transmitter (setting the TXEN to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the transmit Shift Register
and transmit Buffer Register do not contain data to be transmitted. When disabled, the
transmitter will no longer override the TxD pin.
146
ATmega16(L)
2466E–AVR–10/02
ATMEL [ ATMEL ]
