ATmega16(L)
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock
source for the chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register file concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7 shows the internal timing concept for the Register file. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 7. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
Reset and Interrupt
Handling
The AVR provides several different interrupt sources. These interrupts and the separate
reset vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the program counter value, interrupts may be automatically disabled
when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memory Programming” on page 254 for details.
The lowest addresses in the program memory space are by default defined as the Reset
and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 42.
The list also determines the priority levels of the different interrupts. The lower the
address the higher is the priority level. RESET has the highest priority, and next is INT0
11
2466E–AVR–10/02
ATMEL [ ATMEL ]
