ATmega8U2/16U2/32U2
29. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd Rd + Rr
Rd Rd + Rr + C
Rdh:Rdl Rdh:Rdl + K
Rd Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd Rd - K
Rd Rd - Rr - C
Rd Rd - K - C
Rdh:Rdl Rdh:Rdl - K
Rd Rd Rr
Rd Rd K
Z,N,V
Rd Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd Rd Rr
Rd 0xFF Rd
Rd 0x00 Rd
Rd Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd Rd (0xFF - K)
Rd Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd Rd 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd Rd Rd
Z,N,V
CLR
SER
Rd
Rd Rd Rd
Rd 0xFF
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
Indirect Jump to (Z)
PC PC + k + 1
PC Z
None
None
None
None
None
None
None
I
2
2
JMP
k
k
Direct Jump
PC k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC PC + k + 1
4
PC Z
4
k
Direct Subroutine Call
Subroutine Return
PC k
5
PC STACK
5
RETI
Interrupt Return
PC STACK
5
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC PC + 2 or 3
Rd Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd Rr C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC PC + 2 or 3
if (Rr(b)=1) PC PC + 2 or 3
if (P(b)=0) PC PC + 2 or 3
if (P(b)=1) PC PC + 2 or 3
if (SREG(s) = 1) then PCPC+k + 1
if (SREG(s) = 0) then PCPC+k + 1
if (Z = 1) then PC PC + k + 1
if (Z = 0) then PC PC + k + 1
if (C = 1) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (C = 1) then PC PC + k + 1
if (N = 1) then PC PC + k + 1
if (N = 0) then PC PC + k + 1
if (N V= 0) then PC PC + k + 1
if (N V= 1) then PC PC + k + 1
if (H = 1) then PC PC + k + 1
if (H = 0) then PC PC + k + 1
if (T = 1) then PC PC + k + 1
if (T = 0) then PC PC + k + 1
if (V = 1) then PC PC + k + 1
if (V = 0) then PC PC + k + 1
if ( I = 1) then PC PC + k + 1
if ( I = 0) then PC PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
P,b
P,b
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) 1
I/O(P,b) 0
None
None
2
2
1
1
Rd(n+1) Rd(n), Rd(0) 0
Rd(n) Rd(n+1), Rd(7) 0
Z,C,N,V
Z,C,N,V
Logical Shift Right
292
7799D–AVR–11/10
ATMEL [ ATMEL ]
