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ATMEGA16U2-MUR 参数 Datasheet PDF下载

ATMEGA16U2-MUR图片预览
型号: ATMEGA16U2-MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8/16 / 32K Butes [8-bit Microcontroller with 8/16/32K Butes of ISP Flash]
分类和应用: 微控制器异步传输模式PCATM
文件页数/大小: 310 页 / 4432 K
品牌: ATMEL [ ATMEL ]
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ATmega8U2/16U2/32U2  
Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-  
ing the UBRRn value for each mode of operation using an internally generated clock source.  
Table 18-1. Equations for Calculating Baud Rate Register Setting  
Operating Mode  
Equation for Calculating Baud Rate(1)  
Equation for Calculating UBRR Value  
f
OSC  
UBRRn = ----------------------- 1  
16BAUD  
f
OSC  
Asynchronous Normal mode  
(U2Xn = 0)  
BAUD = -----------------------------------------  
16UBRRn + 1  
f
OSC  
UBRRn = -------------------- 1  
8BAUD  
f
OSC  
Asynchronous Double Speed  
mode (U2Xn = 1)  
BAUD = --------------------------------------  
8UBRRn + 1  
f
OSC  
UBRRn = -------------------- 1  
2BAUD  
f
OSC  
Synchronous Master mode  
BAUD = --------------------------------------  
2UBRRn + 1  
Note:  
1. The baud rate is defined to be the transfer rate in bit per second (bps)  
BAUD  
Baud rate (in bits per second, bps)  
fOSC  
System Oscillator clock frequency  
UBRRn  
Contents of the UBRRHn and UBRRLn Registers, (0-4095)  
Some examples of UBRRn values for some system clock frequencies are found in Table 18-9 on  
page 172.  
18.3.2  
Double Speed Operation (U2Xn)  
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has  
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.  
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling  
the transfer rate for asynchronous communication. Note however that the Receiver will in this  
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock  
recovery, and therefore a more accurate baud rate setting and system clock are required when  
this mode is used. For the Transmitter, there are no downsides.  
151  
7799D–AVR–11/10  
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