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ATMEGA169PV-8AU 参数 Datasheet PDF下载

ATMEGA169PV-8AU图片预览
型号: ATMEGA169PV-8AU
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有16K字节的系统内可编程闪存 [Microcontroller with 16K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 390 页 / 3485 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第126页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第127页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第128页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第129页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第131页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第132页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第133页浏览型号ATMEGA169PV-8AU的Datasheet PDF文件第134页  
Table 14-4. Waveform Generation Mode Bit Description(1)  
WGM12  
(CTC1)  
WGM11  
WGM10  
Timer/Counter Mode of  
Update of  
OCR1x at  
TOV1 Flag  
Set on  
Mode  
WGM13  
(PWM11) (PWM10) Operation  
TOP  
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal  
0xFFFF  
0x00FF  
0x01FF  
0x03FF  
OCR1A  
0x00FF  
0x01FF  
0x03FF  
Immediate  
TOP  
MAX  
PWM, Phase Correct, 8-bit  
PWM, Phase Correct, 9-bit  
PWM, Phase Correct, 10-bit  
CTC  
BOTTOM  
BOTTOM  
BOTTOM  
MAX  
TOP  
TOP  
Immediate  
TOP  
Fast PWM, 8-bit  
TOP  
Fast PWM, 9-bit  
TOP  
TOP  
Fast PWM, 10-bit  
TOP  
TOP  
PWM, Phase and Frequency  
Correct  
8
9
1
1
0
0
0
0
0
1
ICR1  
BOTTOM  
BOTTOM  
BOTTOM  
BOTTOM  
PWM, Phase and Frequency  
Correct  
OCR1A  
10  
11  
12  
13  
14  
15  
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
PWM, Phase Correct  
PWM, Phase Correct  
CTC  
ICR1  
OCR1A  
ICR1  
TOP  
TOP  
Immediate  
BOTTOM  
BOTTOM  
MAX  
(Reserved)  
Fast PWM  
ICR1  
OCR1A  
TOP  
TOP  
TOP  
Fast PWM  
TOP  
Note:  
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and  
location of these bits are compatible with previous versions of the timer.  
14.10.2 TCCR1B – Timer/Counter1 Control Register B  
Bit  
7
ICNC1  
R/W  
0
6
ICES1  
R/W  
0
5
4
WGM13  
R/W  
0
3
WGM12  
R/W  
0
2
CS12  
R/W  
0
1
CS11  
R/W  
0
0
CS10  
R/W  
0
(0x81)  
TCCR1B  
Read/Write  
Initial Value  
R
0
• Bit 7 – ICNC1: Input Capture Noise Canceler  
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is  
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four  
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is  
therefore delayed by four Oscillator cycles when the noise canceler is enabled.  
• Bit 6 – ICES1: Input Capture Edge Select  
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture  
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and  
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.  
130  
ATmega169P  
8018A–AVR–03/06  
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