ATmega169P
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 13-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits
are set to a normal or CTC mode (non-PWM).
Table 13-3. Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Table 13-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 13-4. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match, set OC0A at TOP
Set OC0A on compare match, clear OC0A at TOP
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 97
for more details.
Table 13-5 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
rect PWM mode.
Table 13-5. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
Description
0
0
0
1
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when downcounting.
1
1
0
1
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when downcounting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on
page 99 for more details.
• Bit 2:0 – CS02:0: Clock Select
103
8018A–AVR–03/06
ATMEL [ ATMEL ]
