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ATMEGA128-16MC 参数 Datasheet PDF下载

ATMEGA128-16MC图片预览
型号: ATMEGA128-16MC
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有128K字节的系统内可编程闪存 [8-bit Microcontroller with 128K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 31 页 / 308 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA128-16MC的Datasheet PDF文件第8页浏览型号ATMEGA128-16MC的Datasheet PDF文件第9页浏览型号ATMEGA128-16MC的Datasheet PDF文件第10页浏览型号ATMEGA128-16MC的Datasheet PDF文件第11页浏览型号ATMEGA128-16MC的Datasheet PDF文件第13页浏览型号ATMEGA128-16MC的Datasheet PDF文件第14页浏览型号ATMEGA128-16MC的Datasheet PDF文件第15页浏览型号ATMEGA128-16MC的Datasheet PDF文件第16页  
Instruction Set Summary (Continued)  
Mnemonics  
Operands  
Description  
Operation  
Flags  
#Clocks  
BRIE  
BRID  
k
k
Branch if Interrupt Enabled  
Branch if Interrupt Disabled  
if ( I = 1) then PC PC + k + 1  
if ( I = 0) then PC PC + k + 1  
None  
None  
1 / 2  
1 / 2  
DATA TRANSFER INSTRUCTIONS  
MOV  
MOVW  
LDI  
Rd, Rr  
Rd, Rr  
Rd, K  
Move Between Registers  
Copy Register Word  
Rd Rr  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
-
Rd+1:Rd Rr+1:Rr  
Load Immediate  
Rd K  
LD  
Rd, X  
Load Indirect  
Rd (X)  
LD  
Rd, X+  
Rd, - X  
Rd, Y  
Load Indirect and Post-Inc.  
Load Indirect and Pre-Dec.  
Load Indirect  
Rd (X), X X + 1  
X X - 1, Rd (X)  
Rd (Y)  
LD  
LD  
LD  
Rd, Y+  
Rd, - Y  
Rd,Y+q  
Rd, Z  
Load Indirect and Post-Inc.  
Load Indirect and Pre-Dec.  
Load Indirect with Displacement  
Load Indirect  
Rd (Y), Y Y + 1  
Y Y - 1, Rd (Y)  
Rd (Y + q)  
LD  
LDD  
LD  
Rd (Z)  
LD  
Rd, Z+  
Rd, -Z  
Rd, Z+q  
Rd, k  
Load Indirect and Post-Inc.  
Load Indirect and Pre-Dec.  
Load Indirect with Displacement  
Load Direct from SRAM  
Store Indirect  
Rd (Z), Z Z+1  
Z Z - 1, Rd (Z)  
Rd (Z + q)  
LD  
LDD  
LDS  
ST  
Rd (k)  
X, Rr  
(X) Rr  
ST  
X+, Rr  
- X, Rr  
Y, Rr  
Store Indirect and Post-Inc.  
Store Indirect and Pre-Dec.  
Store Indirect  
(X) Rr, X X + 1  
X X - 1, (X) Rr  
(Y) Rr  
ST  
ST  
ST  
Y+, Rr  
- Y, Rr  
Y+q,Rr  
Z, Rr  
Store Indirect and Post-Inc.  
Store Indirect and Pre-Dec.  
Store Indirect with Displacement  
Store Indirect  
(Y) Rr, Y Y + 1  
Y Y - 1, (Y) Rr  
(Y + q) Rr  
ST  
STD  
ST  
(Z) Rr  
ST  
Z+, Rr  
-Z, Rr  
Z+q,Rr  
k, Rr  
Store Indirect and Post-Inc.  
Store Indirect and Pre-Dec.  
Store Indirect with Displacement  
Store Direct to SRAM  
(Z) Rr, Z Z + 1  
Z Z - 1, (Z) Rr  
(Z + q) Rr  
ST  
STD  
STS  
LPM  
LPM  
LPM  
ELPM  
ELPM  
ELPM  
SPM  
IN  
(k) Rr  
Load Program Memory  
Load Program Memory  
Load Program Memory and Post-Inc  
Extended Load Program Memory  
Extended Load Program Memory  
Extended Load Program Memory and Post-Inc  
Store Program Memory  
In Port  
R0 (Z)  
Rd, Z  
Rd (Z)  
Rd, Z+  
Rd (Z), Z Z+1  
R0 (RAMPZ:Z)  
Rd (RAMPZ:Z)  
Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1  
(Z) R1:R0  
Rd, Z  
Rd, Z+  
Rd, P  
P, Rr  
Rr  
Rd P  
1
1
2
2
OUT  
PUSH  
POP  
Out Port  
P Rr  
Push Register on Stack  
Pop Register from Stack  
STACK Rr  
Rd  
Rd STACK  
BIT AND BIT-TEST INSTRUCTIONS  
SBI  
P,b  
P,b  
Rd  
Rd  
Rd  
Rd  
Rd  
Rd  
s
Set Bit in I/O Register  
Clear Bit in I/O Register  
Logical Shift Left  
I/O(P,b) 1  
None  
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI  
I/O(P,b) 0  
None  
LSL  
Rd(n+1) Rd(n), Rd(0) 0  
Z,C,N,V  
LSR  
ROL  
ROR  
ASR  
SWAP  
BSET  
BCLR  
BST  
BLD  
SEC  
CLC  
SEN  
CLN  
SEZ  
CLZ  
SEI  
Logical Shift Right  
Rotate Left Through Carry  
Rotate Right Through Carry  
Arithmetic Shift Right  
Swap Nibbles  
Rd(n) Rd(n+1), Rd(7) 0  
Z,C,N,V  
Rd(0)C,Rd(n+1)Rd(n),CRd(7)  
Z,C,N,V  
Rd(7)C,Rd(n)Rd(n+1),CRd(0)  
Z,C,N,V  
Rd(n) Rd(n+1), n=0..6  
Z,C,N,V  
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)  
None  
Flag Set  
SREG(s) 1  
SREG(s) 0  
T Rr(b)  
Rd(b) T  
C 1  
SREG(s)  
s
Flag Clear  
SREG(s)  
Rr, b  
Rd, b  
Bit Store from Register to T  
Bit load from T to Register  
Set Carry  
T
None  
C
C
N
N
Z
Z
I
Clear Carry  
C 0  
Set Negative Flag  
Clear Negative Flag  
Set Zero Flag  
N 1  
N 0  
Z 1  
Clear Zero Flag  
Z 0  
Global Interrupt Enable  
Global Interrupt Disable  
Set Signed Test Flag  
Clear Signed Test Flag  
I 1  
CLI  
I 0  
I
SES  
CLS  
S 1  
S
S
S 0  
12  
ATmega128  
2467OS–AVR–10/06  
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