ATmega128(L)
Table 48. Interrupt Sense Control(1)
ISCn1
ISCn0 Description
0
1
1
1
0
1
Reserved
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
Note:
1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Table 49. Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min
Minimum pulse width for
Typ
Max
Units
tINT
50
ns
asynchronous external interrupt
External Interrupt
Control Register B –
EICRB
Bit
7
ISC71
R/W
0
6
ISC70
R/W
0
5
ISC61
R/W
0
4
ISC60
R/W
0
3
ISC51
R/W
0
2
ISC50
R/W
0
1
0
ISC41
R/W
0
ISC40
R/W
0
EICRB
Read/Write
Initial Value
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 50. The value on the INT7:4 pins are sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is
enabled. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low.
Table 50. Interrupt Sense Control(1)
ISCn1 ISCn0 Description
0
0
0
1
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt
request.
1
0
The rising edge between two samples of INTn generates an interrupt
request.
1
1
Note:
1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
External Interrupt
Mask Register –
EIMSK
Bit
7
6
5
4
3
2
1
0
IINT0
R/W
0
INT7
R/W
0
INT6
R/W
0
INT5
R/W
0
INT4
R/W
0
INT3
R/W
0
INT2
R/W
0
INT1
R/W
0
EIMSK
Read/Write
Initial Value
• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable
91
2467P–AVR–08/07
ATMEL [ ATMEL ]
