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ATMEGA128L-8AL 参数 Datasheet PDF下载

ATMEGA128L-8AL图片预览
型号: ATMEGA128L-8AL
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 391 页 / 6192 K
品牌: ATMEL [ ATMEL ]
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ATmega128(L)  
Power  
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving  
power. The AVR provides various sleep modes allowing the user to tailor the power consump-  
tion to the application’s requirements.  
Management  
and Sleep  
Modes  
To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a  
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register  
select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or  
Extended Standby) will be activated by the SLEEP instruction. See Table 17 for a summary. If  
an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is  
then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and  
resumes execution from the instruction following SLEEP. The contents of the register file and  
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,  
the MCU wakes up and executes from the Reset Vector.  
Figure 18 on page 36 presents the different clock systems in the ATmega128, and their distribu-  
tion. The figure is helpful in selecting an appropriate sleep mode.  
MCU Control Register The MCU Control Register contains control bits for power management.  
– MCUCR  
Bit  
7
6
SRW10  
R/W  
0
5
SE  
R/W  
0
4
3
2
1
IVSEL  
R/W  
0
0
IVCE  
R/W  
0
SRE  
R/W  
0
SM1  
R/W  
0
SM0  
R/W  
0
SM2  
R/W  
0
MCUCR  
Read/Write  
Initial Value  
• Bit 5 – SE: Sleep Enable  
The SE bit must be written to logic one to make the MCU enter the Sleep mode when the  
SLEEP instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-  
grammers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the  
execution of the SLEEP instruction and to clear it immediately after waking up.  
• Bits 4..2 – SM2..0: Sleep Mode Select Bits 2, 1, and 0  
These bits select between the six available sleep modes as shown in Table 17.  
Table 17. Sleep Mode Select  
SM2  
SM1  
SM0  
Sleep Mode  
Idle  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC Noise Reduction  
Power-down  
Power-save  
Reserved  
Reserved  
Standby(1)  
Extended Standby(1)  
Note:  
1. Standby mode and Extended Standby mode are only available with external crystals or  
resonators.  
45  
2467P–AVR–08/07  
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