ATmega128(L)
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
T1
T2
T3
T4
T5
T6
T7
System Clock (CLKCPU
)
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
Address
Data
Address
Address
XX
DA7:0 (XMBK = 0) Prev. data
DA7:0 (XMBK = 1) Prev. data
RD
Data
Data
Address
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
XMEM Register
Description
MCU Control Register
– MCUCR
Bit
7
6
SRW10
R/W
0
5
SE
R/W
0
4
3
2
1
IVSEL
R/W
0
0
IVCE
R/W
0
SRE
R/W
0
SM1
R/W
0
SM0
R/W
0
SM2
R/W
0
MCUCR
Read/Write
Initial Value
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
• Bit 6 – SRW10: Wait-state Select Bit
For a detailed description in non-ATmega103 compatibility mode, see common description for
the SRWn bits below (XMCRA description). In ATmega103 compatibility mode, writing SRW10
to one enables the wait-state and one extra cycle is added during read/write strobe as shown in
Figure 14.
External Memory
Control Register A –
XMCRA
Bit
7
–
6
SRL2
R/W
0
5
SRL1
R/W
0
4
SRL0
R/W
0
3
SRW01
R/W
0
2
SRW00
R/W
0
1
SRW11
R/W
0
0
–
XMCRA
Read/Write
Initial Value
R
0
R
0
• Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
31
2467P–AVR–08/07
ATMEL [ ATMEL ]
