ATmega128(L)
Data Memory Access
Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.
Figure 10. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address valid
Compute Address
Address
Data
WR
Data
RD
Memory access instruction
Next instruction
EEPROM Data
Memory
The ATmega128 contains 4K bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
“Memory Programming” on page 286 contains a detailed description on EEPROM programming
in SPI, JTAG, or Parallel Programming mode
EEPROM Read/Write
Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 2. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-
ing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
EEPROM Address
Register – EEARH and
EEARL
Bit
15
14
13
12
11
EEAR11
EEAR3
3
10
EEAR10
EEAR2
2
9
EEAR9
EEAR1
1
8
EEAR8
EEAR0
0
–
–
–
–
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEARL
7
R
6
R
5
R
4
R
Read/Write
Initial Value
R/W
R/W
X
R/W
R/W
X
R/W
R/W
X
R/W
R/W
X
R/W
0
R/W
0
R/W
0
R/W
0
X
X
X
X
X
X
X
X
• Bits 15..12 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bits 11..0 – EEAR11..0: EEPROM Address
21
2467P–AVR–08/07
ATMEL [ ATMEL ]
