Modes of
Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is
defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output
mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the waveform generation mode bits do. The COMnx1:0 bits control whether the PWM
output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM
modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a
compare match (See “Compare Match Output Unit” on page 123.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 131.
Normal Mode
The simplest mode of operation is the normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in normal mode is not recommended, since this will occupy
too much of the CPU time.
Clear Timer on
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register
Compare Match (CTC) are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
Mode
the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =
12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the opera-
tion of counting external events.
The timing diagram for the CTC mode is shown in Figure 51. The counter value (TCNTn)
increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)
is cleared.
Figure 51. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(Toggle)
(COMnA1:0 = 1)
1
2
3
4
Period
124
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
