ATmega128(L)
Table 52. Waveform Generation Mode Bit Description
WGM01(1) WGM00(1) Timer/Counter
Update of
TOV0 Flag
Set on
Mode
(CTC0)
(PWM0)
Mode of Operation TOP
OCR0 at
Immediate
TOP
0
1
0
0
0
1
Normal
0xFF
0xFF
MAX
PWM, Phase
Correct
BOTTOM
2
3
1
1
0
1
CTC
OCR0 Immediate
0xFF BOTTOM
MAX
MAX
Fast PWM
Note:
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set
in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0
bit setting. Table 53 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a
normal or CTC mode (non-PWM).
Table 53. Compare Output Mode, non-PWM Mode
COM01
COM00
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0 disconnected.
Toggle OC0 on compare match
Clear OC0 on compare match
Set OC0 on compare match
Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 54. Compare Output Mode, Fast PWM Mode(1)
COM01
COM00
Description
0
0
1
0
1
0
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match, set OC0 at BOTTOM,
(non-inverting mode)
1
1
Set OC0 on compare match, clear OC0 at BOTTOM,
(inverting mode)
Note:
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 99
for more details.
Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct
PWM mode.
105
2467P–AVR–08/07
ATMEL [ ATMEL ]
